1. Field of the Invention
The present invention relates generally to a method of forming a MOS semiconductor device having a localized anti-punchthrough region, and more particularly to a method of forming a MOS semiconductor device having a localized anti-punchthrough region which is not in contact with source/drain regions to reduce source/drain junction capacitance.
2. Technical Background
A conventional method for fabricating a MOS semiconductor device having an anti-punchthrough region is illustrated in FIGS. 1A-1C in cross-sectional views. Referring to FIG. 1A, P-type substrate 1 is first implanted with P-type impurities (e.g., Boron) to form anti-punchthrough region 10 beneath the surface of the substrate 1. Referring next to FIG. 1B, implanted P-type substrate 1 is then subjected to oxidation to form a gate oxide layer 12 thereon. Polysilicon layer 14 is deposited on oxide layer 12. It is noted that polysilicon layer 14 is typically doped with impurities to increase its conductivity. Polysilicon layer 14 and oxide layer 12 are thereafter patterned and etched to form a corresponding gate electrode 14 and a gate oxide layer 12.
Referring now to FIG. 1C, an ion implantation process is then conducted to implant N-type impurities, such as arsenic and phosphorus, into P-type substrate 1 to form N-type heavily-doped regions 16 which constitute source/drain regions. Gate electrode 14 is used as a mask in this process.
However, as shown in FIGS. 1A-1C, anti-punchthrough region 10 fabricated by the conventional method is not localized, but spreads over all the area beneath the gate region, and therefore is in contact with N-type heavily-doped regions 16. Accordingly, the junction capacitance of the source/drain regions of the resulting MOS device increases, and thus reducing device operational speed.
The anti-punchthrough region is originally formed for the purpose of narrowing the depletion region when the source/drain region is operated in reverse-biased condition so as to attain anti-punchthrough. However, as the anti-punchthrough region formed by conventional method becomes not localized, the junction capacitance of the source/drain regions is increased and the operational speed of the device is reduced.
For the foregoing reasons, there is a need to have a method of forming a MOS device having a localized anti-punchthrough region, with reduced source/drain junction capacitance for high speed submicron device applications.